This invention relates to an event based test system for testing semiconductor devices, and more particularly, to an event based test system which can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory.
In testing semiconductor devices such as ICs and LSIs (Large Scale Integrated circuits) by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test signals. The output signals are strobed or sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly or not.
For improving test efficiency, scan design is one of approaches established in integrated circuit design (design for test). The present invention is directed to an event based test system for testing IC devices with or without such scan design. Before going into further details of the problems involved in a conventional semiconductor test system for generating scan vectors for the scan design IC devices under test, brief description will be made in the following as to an, example of test signals and associated circuit structure in the semiconductor test system.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based (or cyclized) test system. Another type of test system is called an event based test system wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. The present invention is directed to such an event based semiconductor test system.
In an event based test system, notion of events are employed, which are any changes of the logic state in the signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals, or timing edges of strobe signals. The timings of the events are defined with respect to a time length from a reference time point. Typically, such a reference time point is a timing of the previous (last) event. Alternatively, such a reference time point is a fixed start time common to all of the events.
In an event based test system or an event tester, since the timing data in a timing memory (event memory) does not need to include complicated information regarding waveform, vector, delay and etc., relative to each and every test cycle, the description of the timing data can be dramatically simplified. However, it generally requires a large memory capacity for storing the timing data in the event memory.
In an event based test system, the timing (event) data for each event stored in an event memory is expressed, for example, by a time difference between the current event and the last event. For producing high resolution timings, the time length (delay value) between the events is defined by a combination of an integer multiple of a reference clock cycle (integer part or event count) and a fraction of the reference clock cycle (fractional part or event vernier). A timing relationship between the event count and the event vernier is shown in timing charts of FIGS. 3A-3E. In this example, a reference clock (master clock or system clock) of FIG. 3A has a clock cycle (hereafter also referred to as xe2x80x9cperiodxe2x80x9d) T. Event 0, Event 1 and Event 2 are related in timings as shown in FIG. 3C.
To describe Event 1 with reference to Event 0, a time difference (delay) xcex94V1 between the two events is defined in an event memory. The timing of Event 2 is defined by a time difference (delay) xcex94V2 from Event 1. Similarly, the timing of Event 3 in FIG. 3E is defined by a time difference (delay) xcex94V3 from Event 3. In the event test system, the timing data in the event memory is read out and summed up to all of the previous events to produce an ultimate timing of the current event.
Therefore, in the example of FIG. 3C, to produce Event 1, the timing relationship of FIG. 3B is used in which N1T denotes the event count which is N1 times of the reference clock period T and xcex941T denotes the event vernier which is a fraction of the reference clock period T. Similarly to produce Event 3 in FIG. 3E with reference to Event 0, the timing data for all prior events are summed up to produce an overall time difference expressed by N3T+xcex943T wherein N3T denotes the event count which is N3 times the reference clock period T and xcex943T denotes the event vernier which is a fraction of the reference clock period T.
In actual device testing, a test signal for a certain pin of the device under test may not change for a long period of time such as several hundred milliseconds while test signals for most other pins change at much higher rates such as several ten or hundred nanoseconds. This means that the time length between the two adjacent events can be in a very wide variety, requiring large bits of data to describe the maximum possible time length. Since a semiconductor test system is a large system having, for example, several hundred test channels (pins), where each test channel includes an event memory, it is desirable to minimize the capacity of the event memory to decrease the overall cost of the test system.
Such memory reduction is especially important in storing test vectors for testing scan design IC devices. Scan design is well established methodology in the IC design to make the IC device easily testable (design for test). In full-scan methodology, scan flip-flops are used in the circuit instead of ordinary D flip-flop or J-K flip-flop. The scan flip-flop contains a multiplexer that allows them to connect in a shift register mode during the test.
FIG. 6 shows an example of basic scan structure in an IC device incorporating the scan design concept. In this example, a pair of scan flip-flop 132 and a switch SW (multiplexer) and a pair of scan flip-flop 134 and a switch SW (multiplexer) are shown to test a combinational logic in the semiconductor device under test. This basic structure in the scan design is known in the art, and more detailed description is given in xe2x80x9cDigital Hardware Testingxe2x80x9d, Rochit Rajsuman, Artech House, 1992, pp197-238. In the scan design, the general steps of testing are:
(1) Connect flip-flops in shift register (using test mode) and serially shift-in (scan-in) a test vector.
(2) Switch to normal operational mode and thus apply the value in flip-flops (test vector) to the circuit and capture response in the flip-flops.
(3) Switch back to the test mode and serially shift-out (scan-out) the response for evaluation purpose.
In general, the number of scan vectors is quite large such as 16-million to 128-million. In an event based test system noted above, the test vectors are stored based upon change-in-value (event) and the time when the event occurs. This time information is generally defined with respect to a reference time such as time of power-on or clock start time or with respect to the previous event such as shown in FIGS. 3A-3E. To store large number of-scan vectors (such as 128-million vectors) in this format requires extremely large amount of physical memory.
Therefore, it is an object of the present invention to provide a scan vector generation method and apparatus in an event based test system for testing an IC device having a scan architecture with use of a small capacity event memory.
In the present invention, the event based test system can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory. The event based test system includes an event memory for storing timing data and event type data of each event where the timing data is expressed by a plurality (log2N) of data bits for defining one test vector, an event generator for generating an event with use of the timing data and the event type data from the event memory, and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors by detecting the scan mode when the event type data from the event memory indicating a predetermined word. In the test system, each bit of the plurality (log2N) of data bits in the event memory defines each scan vector, and N data bits are provided to the event generator in a series fashion, thereby producing 2N scan vectors at each access of the event memory.
According to the present invention, the event based test system is capable of producing the scan vectors with use of log2N-bit data in a parallel form from the event memory and converts the log2N-bit data to serial data of 2N-bit, thereby producing 2N scan vectors with use of memory locations corresponding to one test vector.
In the event based test system of the present invention, the timing data in the event memory is comprised of delay count data which is formed with an integer multiple of a reference clock period (integral part data) and delay vernier data which is formed with a fraction of the reference clock period (fractional part data). Further, the timing data for producing the scan vectors is stored in a register provided separately from the event memory and is supplied to the event generator in the scan mode.
The mode change circuit is comprised of a parallel to serial converter for converting the plurality (log2N) of data bits from the event memory at each access to 2N-bit serial data and a multiplexer for selecting the 2N-bit serial data from the parallel to serial converter and providing the 2N-bit serial data to the event generator during the scan mode for producing the scan vectors.